By: Michael Feldman

AMD’s Zen 2 EPYC processor, codenamed “Rome,” has yet to be released, but the chip has already staked out a future home in what will be one of the largest supercomputers in Europe. The upcoming system, known as Hawk, will be built by Hewlett Packard Enterprise and installed at the High-Performance Computing Center of the University of Stuttgart, also known as HLRS.

At 24 peak petaflops, Hawk will be about three-and-a-half times more powerful than Hazel Hen, HLRS’s current flagship supercomputer. The new system will be comprised of 5,000 nodes equipped with 64-core Rome processors. Assuming we’re talking dual-socket nodes here, each chip is set to deliver around 2.4 teraflops of peak double precision performance. Up until just a couple years ago, that kind of number crunching was only available in a very expensive GPU or Xeon Phi.

HLRS says that when Hawk comes online, it will be the world’s fastest supercomputer for industrial production. Most of the center’s commercial partners are engineering companies of various stripes and are awarded time on HLRS supercomputers to help design their products. At the moment, one of the more prominent industrial partners is Porsche, who use HLRS for a number of their engineering simulations. The center also supports scientific research in areas like health, climate, and energy.

As a result of this application profile, a lot of the codes running through the supercomputer machinery at HLRS are using computational fluid dynamics (CFD) and molecular dynamics (MD) kernels. And this offers at least one hint why the gang at Stuttgart opted for a system with Rome processors: CFD and MD codes demand a good deal of memory bandwidth and EPYC silicon has proven to be particularly generous with it.

Bastian Koller, who heads up the Applications and Visualization group at HLRS, said that when they look at benchmarks to use for their upcoming systems, the High Performance Conjugate Gradients (HPCG) suite is “more interesting” to them than Linpack. HPCG is heavily influenced by memory performance, so it tends to favor systems that are offer it in greater abundance. They also run their own codes to help evaluate future systems, and according to Koller, the Rome-powered setup offered the best match overall, performance-wise.

There are probably other elements of the HPE supercomputer that contributed to the HLRS win, but since this platform has yet to be announced or even described, it’s difficult to speculate on what that might entail.

In any case, the introduction of the second-generation EPYC in 2019 promises to be much more significant event for HPC consumers than the 2017 release of the original. There are a handful of HPC clusters with first-generation EPYCs now being installed, but this is occurring over a year after the chips were on the market. As it stands today, there is not a single EPYC supercomputer on the TOP500 list, unless you count the Advanced Computing System (PreE) system from Sugon. It uses Dhyana CPUs, which is a licensed implementation of the EPYC 7501.

The one thing that was missing in the first-generation EPYC was a generous number of flops, at least relative to Intel’s Skylake Xeon scalable processor. The top-of-the-line Skylake chips offer something north of 2 teraflops of peak performance, while the corresponding AMD EPYC CPUs provide less than half of that. That’s something that has apparently been rectified in Rome.

Hawk is projected to cost €38 million and if everything goes according to plan, will be installed toward the end of 2019. It’s expected go into full production in 2020.